فهرست نشریات علمی دسترسی آزاد ایران

Dynamic circuits offer a promising solution due to their low power consumption and high performance compared to static ones. However, dynamic circuits have their limitations, particularly in terms of robustness. This article presents a new dynamic circuit that reduces power consumption and delays for high-fan-in OR gates without significant loss of robustness.  In the new dynamic circuit, the pull-down network (PDN) is split to increase the speed. Furthermore, employing a reference circuit decreases the conflict current that occurs between the PDN and keeper transistors. For this purpose, the reference circuit replicates the leakage current of the PDN. Therefore, the power and delay of the presented circuit are reduced. In addition, the sub-threshold leakage current and hence the leakage power are decreased in the PDN because of the body effect. The results of simulating high fan-in OR gates in a 90nm CMOS technology show 45% and 53% reduction in delay and power consumption, respectively while maintaining the same level of robustness as the conventional circuit for 64 inputs OR gates. Moreover, the tag comparator designed with the presented circuit shows a 2.65 times improvement in the figure of merit compared to the conventional design.