A Procedure to Compare CNTFET and CMOS Technologies through the Design of a SRAM Cell: A Review
نویسندگان
1 Electronic Devices Laboratory, Department of Electrical and Information Engineering, Polytechnic University of Bari, 70126, Bari, Italy
2 Electronic Devices Laboratory, Department of Electrical and Information Engineering, Polytechnic University of Bari, 70126, Bari, Italy
doi
10.22034/ijnn.2024.2021428.2472چکیده
In this paper we review in depth a procedure to compare the performance of CNTFET and MOSFET devices operating in sub-threshold region for ultra-low power applications. This aim is obtained through the design of a SRAM cell. The first design is based on our CNTFET model, while for the second one we use the BSIM4 model of the ADS library. At last the comparison between the two considered technologies are quantitatively presented, showing and discussing the improvements obtained with CNTFET technology. All simulations are carried out using the software Advanced Design System (ADS), which is compatible with the Verilog-A programming language, avoiding so the problems presented in SPICE used in previous designs proposed in literature.
