Spacer Engineered Asymmetrical Dual Gate Tunnel Field Effect Transistor with Stacked Dielectric Materials for Low Power Applications
نویسندگان
1 Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Green Fields, Vaddeswaram, Andhra Pradesh-522502, India
2 Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Green Fields, Vaddeswaram, Andhra Pradesh-522502, India
3 Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Green Fields, Vaddeswaram, Andhra Pradesh-522502, India
4 Department of Electronics and Communication Engineering, Graphic Era (Deemed to be University), Dehradun-248002, India
doi
10.5829/ije.2025.38.06c.02چکیده
The Gate Overlap and Underlap Spacer dielectric material Tunnel Field-Effect Transistor (GOUS-TFET) is proposed in this work, using 10nm technology. The device utilizes a high-k dielectric material, being hafnium oxide(HfO2) and its optimization considers various parameters, including the spacer dielectric, overlap, and underlap, which plays a crucial role in determining the device performance parameters. The overlap and underlap of HfO2 spacer dielectric material and asymmetrical gate enable precise control over the tunneling region, optimize threshold voltage, reduce leakage, and improve the subthreshold swing.This work investigates the impact of spacer dielectric configurations on advanced TFET through simulations and analyses using the Silvaco TCAD ATLAS tool. The spacer dielectric, positioned between the source and gate regions of the TFET device significantly influences device characteristics such as reduced leakage current of 7.12 × 10-13 (A/µm), subthreshold swing of 71 Mv/decade, enhances the on-state current of 3.16 × 10-4 (A/µm), and threshold voltage of 0.98 (v). Based on improved electrical parameters and drain current characteristics of GOUS-TFET, the proposed device is extensively used in low-power applications.
