On-Chip Interconnection Network with an Ecient Parallel Bu er Structure and Generic Trac Model
نویسندگان
1 Research Center,Queens University
2 Department of Electrical Engineering,University of California
doi
چکیده
In this paper, we present two important topics indirectly related to the design and simulated analysis of Network-on-Chip (NoC) architectures. In order to enhance the performance of the baseline router to achieve maximum throughput,a new parallel bu er architecture and its management scheme are introduced. By adopting an adjustable architecture that integrates a parallel bu er with each incoming port, the design complexity and its utilization can be optimized. By utilizing simulation-based performance evaluation and comparison with previous NoC architectures, its eciency and superiority are proven. One of the key areas of research addressed in this work is to nd more realistic trac models in order to properly test the bu er management schemes proposed in this work. Therefore, we introduce a generic trac model for on-chip interconnection networks that is superior to previous techniques for NoC architectural performance evaluation. Our trac model is based on three empirically-derived statistical characteristics using temporal and spatial distributions. With captured parameters, accurate trac patterns can be generated recursively to show similar statistical characteristics of the observed on-chip networks.
