An efficient parallel critical path tracing for path delay fault simulation

نویسندگان
patel renuka ID 1
fernandes thais maria freire ID 2
prajapati nipa ID 3
souza ricardo alves de ID 4
asarsa shekhar ID 5

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doi
10.22052/scj.2022.246420.1068
چکیده

Delay fault simulation is the most general method that is used to assess the quality of generated test sets. Path delay fault is one of the most frequently used delay fault models. Path delay fault simulation is a time-consuming operation, especially for today's complex digital circuits. In this work, a novel critical path tracing algorithm is proposed for parallel path delay fault simulation. The obtained outcomes denote 489 times average speedup compared with the traditional path tracing, as well as 186 times average speed-up in comparison with the latest reported results of previous studies.

کلیدواژه‌ها
حسین صباغیان بیدگلی1, احمد احترام2, حسین قسوری2, مجید دلشاد3, شاهین حسابی4, Path delay fault, Fault simulation, Critical path tracing, Robust path, Non-robust path, Hossein Sabaghian-Bidgoli1, Ahmad Ehteram2, Hossein Ghasvari2, Majid Delshad3, Shaahin Hessabi4