Vertical Tunneling Transistor Based on Gr-hBN-χ3 Borophene Heterostructure with AA Stack
نویسندگان
1 Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran
2 Department of Electrical Engineering, Sharif University of Technology, Tehran, Iran
3 Department of Electrical Engineering, Arak Branch, Islamic Azad University, Arak, Iran
doi
10.22060/eej.2025.23756.5632چکیده
In this paper, the electronic properties of vertical Gr-hBN-χ3 borophene heterostructure (AA stack between Gr and hBN layers), i.e., (Gr-hBN-χ3_AA), have been investigated by density functional theory (DFT). By using the tight-binding (TB) model and least-square fitting for TB and DFT band structures, optimal TB parameters are calculated. By exploiting the non-equilibrium Green function technique and capacitive model, we have investigated the vertical tunneling transistor (VTFET) based on Gr-hBN-χ3_AA. Also, the figure of merit (FOM) of the device, such as the ION/IOFF ratio, subthreshold swing, and intrinsic gate-delay time, has been extracted. We have concluded that decreasing the width of the graphene nanoribbon improves the switching ratio, subthreshold swing, and gate-delay time. Also, compared to previous work (VTFET based on Gr-hBN-χ3_AB), it is seen that changing the stack between Gr and hBN layers has little effect on the FOM of the device. The gate-delay time of the device is 0.011 ps at room temperature.
