Fast and Efficient Hardware Implementation of 2D Gabor Filter for a Biologically-Inspired Visual Processing Algorithm
نویسندگان
1 Electrical Engineering Department, Faculty of Engineering, Islamic Azad University, Science and Research Branch, Tehran, Iran.
2 Electrical Engineering Department, Faculty of Engineering, Islamic Azad University, Science and Research Branch, Tehran, Iran.
3 Artificial Intelligence Department, Faculty of Computer Engineering, Shahid Rajaee Teacher Training University; Tehran, Iran. School of Cognitive Sciences, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran.
4 Communication Engineering Department, Faculty of Electrical Engineering, Shahid Rajaee Teacher Training University, Tehran, Iran. School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran.
doi
10.22061/jecei.2020.7548.404چکیده
Background and Objectives: Programmable logic devices, such as Field Programmable Gate Arrays, are well-suited for implementing biologically-inspired visual processing algorithms and among those algorithms is HMAX model. This model mimics the feedforward path of object recognition in the visual cortex. Methods: HMAX includes several layers and its most computation intensive stage could be the S1 layer which applies 64 2D Gabor filters with various scales and orientations on the input image. A Gabor filter is the product of a Gaussian window and a sinusoid function. Using the separability property in the Gabor filter in the 0° and 90° directions and assuming the isotropic filter in the 45° and 135° directions, a 2D Gabor filter converts to two more efficient 1D filters.Results: The current paper presents a novel hardware architecture for the S1 layer of the HMAX model, in which a 1D Gabor filter is utilized twice to create a 2D filter. Using the even or odd symmetry properties in the Gabor filter coefficients reduce the required number of multipliers by about 50%. The normalization value in every input image location is also calculated simultaneously. The implementation of this architecture on the Xilinx Virtex-6 family shows a 2.83ms delay for a 128×128 pixel input image that is a 1.86X-speedup relative to the last best implementation.Conclusion: In this study, a hardware architecture is proposed to realize the S1 layer of the HMAX model. Using the property of separability and symmetry in filter coefficients saves significant resources, especially in DSP48 blocks.
