فهرست نشریات علمی دسترسی آزاد ایران

Abstract: For the first time, in this research, we introduce a junctionless tunneling FET (J-TFET) on a uniform p+ starting junctionless FET to realize appreciable immunity against inherent high ambipolar current ( I amb ). So, we utilize two isolated gates with appropriate workfunctions over the channel and drain regions to create P+IP+N+ charge distribution. This structure utilizes a space between the gate-drain electrodes ( S GD ), to provide a P+IP+N+ structure thanks to the effective electrons depletion on the drain side. Increasing the S GD , further effectively pulls up the bands near the interface between the channel-drain regions, widens the tunneling width for tunneling to occur, and thus in turn reduces the I amb from 5.37×10-7 A/µm to 1.14×10-14 A/µm. Thus, we point out that the proposed J-TFET can obtain on-current that satisfies the expectation of logic applications with high performance and I off that meets the specifications of low power characteristics, a phenomenon that is rarely accessible with conventional TFETs.