Voltage Difference Technique in Junctionless Tunneling FET for Suppression of Ambipolar Conduction

نویسندگان
doi
10.30495/jopn.2023.32088.1294
چکیده

Abstract: A detailed study of a novel configuration for junctionless tunneling FET (J-TFET) with extremely low off- ( I off ) and ambipolar current ( I amb ) is reported in this paper. In order to achieve desirable on/off current ratio ( I on /I off ), we have employed voltage difference technique on the gate electrode based on the potential distribution benefits. Main and side gates with an optimum voltage difference creates a stepped potential profile along the channel. This raises the drain side’s bands, reduces the electric field, puts restriction on the flow of charge carriers, and finally remarkable reduction of I amb from 6.52×10 -10 A/µm to 1.14×10 -17 A/µm. Also an extremely low subthreshold swing ( SS ) (22 mV/dec) is achieved thanks to the sharp transition from off- to the on-state. Finally we have investigated the electrical performance of the proposed device for sub-30 nm channel length to examine its immunity against short channel effects. Therefore, our approach renders the novel structure more desirable for the future low power applications.